QuickLogic Launches Aurora PRO Tool to Boost Chip Design Speed and Efficiency

QuickLogic Corporation (NASDAQ:QUIK), a leader in embedded FPGA (eFPGA) Hard IP, ruggedized FPGAs, and endpoint AI solutions, today unveiled Aurora PRO, a powerful evolution of its Aurora FPGA design tool. Integrating Synopsys Synplify® FPGA synthesis, Aurora PRO empowers engineers to achieve greater resource utilization and maximum frequency (Fmax).

Building on the robust Aurora Software Tool Suite, known for its intuitive device creation flow and proven Place & Route process, Aurora PRO introduces key advancements that further optimize performance and design efficiency.

Improved Performance with Synopsys Synplify® FPGA Synthesis

Aurora PRO incorporates the widely adopted industry standard Synopsys Synplify® FPGA design synthesis optimized for QuickLogic's eFPGA hard IP. This integration delivers up to a 50% improvement in resource utilization, as demonstrated by customer designs achieving over 96% LUT utilization. The combination of Synplify and Aurora also improves performance with average frequency increases of up to 10% for eFPGA designs translating directly into improved system performance. This integration allows engineers to pack more functionality into smaller silicon footprints, reduce power consumption, and achieve critical timing closure faster, ultimately leading to more competitive and robust products.

Optimized for QuickLogic's eFPGA Architecture

The integration of Synplify® is tailored to QuickLogic's eFPGA architecture, with optimizations for embedded carry chains, BRAM, and DSP blocks. This targeted synthesis significantly reduces critical path delays and accelerates design convergence, delivering superior quality of results (QoR) which are critical for various industries.

Streamlined User Interface and Controls

Aurora PRO's redesigned user interface provides a truly seamless experience, integrating Synplify® synthesis directly within the Aurora GUI. This intuitive environment allows engineers to effortlessly manage complex area vs. timing trade-offs, accelerating experimentation, and enabling faster iterations to achieve optimal design parameters with greater flexibility.